1. Field of the Invention
The present invention relates generally to computer systems and more particularly to bandwidth utilization of a memory bus in a computer system wherein a bus master prefetch unit responds to a bus master request for accessing a first line of data by fetching a second adjacent line of data and storing it in a prefetch buffer for later access subsequent to accessing the first line.
2. Description of the Prior Art
In today's information based society, computer systems are widely used, for example in enterprises, homes, universities, manufacturing units, government organizations and research centers. Modern day computers need to perform several tasks simultaneously. These tasks may include execution of large and sophisticated applications that benefit from faster computer systems with higher processing speed.
The overall processing speed of a computer system depends on the speed of its various components. Today's computers employ high-speed processing units. However, each component of a computer system can limit the overall speed of the system. One such component that limits the processing speed of a computer system is the memory bus that connects a memory device, for example an external DRAM, to the other components of the computer system.
The memory bus may have many masters which may be controllers, for accessing the memory device through the memory bus. Several applications can access the memory device through the bus masters. Bus masters include various internal hardware components such as processors, Direct Memory Access (DMA) controllers and so forth. All the masters of the memory bus are connected to the memory bus through a memory controller. The memory controller arbitrates over the bus masters for access to the memory device by prioritizing requests from various bus masters according to predefined rules.
Requests for access to the memory device are queued in the memory controller. The memory controller allows the masters to access the memory device one by one. Each request has to wait for its turn to gain access to the memory device. This limits the overall speed of processing. Further, there are times when there is no request in queue. In such times, the memory bus remains idle.
High bandwidth devices are very common in today's applications for most computer peripherals and consumer electronic devices. High bandwidth devices include masters like the USB and the display driver. These devices have specific bandwidth and data rate requirements for efficient performance and functionality of the device. Lack of bandwidth in accessing the memory device hurts the actual system performance.
Several attempts have been made to utilize this idle time of the memory bus to optimize the bandwidth usage of the memory bus. In order to increase the overall speed of bus master accesses to the memory device, the concept of prefetching of data is employed. Prefetching of data means getting data from slow external memory devices ahead of time. This is done so that a resource requesting data will not have to wait for the data to be fed from the memory device when it is actually needed. This reduces the overall latency of reading data from the external memory.
Several patents exist that deal with optimization of the memory bus bandwidth. One such patent is U.S. Pat. No. 5,881,248, titled “System and Method for Optimizing System Bus Bandwidth in an Embedded Communication System” assigned to Advanced Micro Devices, Inc. This patent relates to a communication system that includes a receive buffer, a memory, a CPU, a direct memory access (DMA) controller and a bus arbitrator. Each of these components is coupled to the memory bus. The buffer operates to generate a low or high priority DMA transfer request. When the buffer generates a low priority DMA request, the DMA controller and/or bus determine if the system bus is otherwise not being utilized. If the system bus if not being utilized, the DMA transfer is allowed. Thus, the system utilizes the idle time of the memory bus.
Another patent that deals with the optimization of memory bus bandwidth is U.S. Pat. No. 6,233,656, titled “Bandwidth Optimization Cache”, assigned to LSI Logic Corporation. The patent relates to optimizing bus bandwidth utilization in an environment where bus accesses range in size from a single word to multi-word burst accesses. The system achieves this by prefetching and caching additional words when responding to a single word access request. Prefetching of data means retrieving and storing data even if there is no request for the data. This data may be served to a requester if it requests the data at a future later time. The invention includes receiving a read request from a client, checking the contents of a cache to determine whether the cache contains the information sought in the read request and returning the information from the cache if a cache hit results. If the data is not in the cache, a bus transaction is initiated by fetching a block of memory containing the information from a memory store, sending the information to the client, and caching the additional remaining information included with the fetched block of memory. The system disclosed in the above mentioned patent includes a cache memory, which stores a chunk of data that includes the requested data. This cache based prefetch mechanism concentrates on speeding up data access for the requester that the Cache services. Cache based mechanisms, however, do not optimize the external memory bus bandwidth utilization.
Another disclosure that deals with the optimization of memory bus bandwidth is US Patent Application Number 20030126355, entitled “Distributed Memory Module Cache Prefetch”. The disclosure relates to a distributed memory module cache including a tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to a memory module. The data cache and associated logic are located in one or more buffer components in each of the memory modules. The disclosed system has the ability to read a current line of data out of a memory module DRAM and to load the next cache line of data into the memory module data cache. This allows the utilization of excess DRAM interconnect bandwidth, while preserving limited memory bus bandwidth.
However, the existing systems do not effectively optimize the memory bus bandwidth for bus master accesses using the concept of prefetching. Further, external memory devices such as SDRAM and DDR SDRAM organize data in a set of two or more banks. Each bank again is organized into a set of rows and columns. Every time a data is read from this memory, the particular row of the bank, which has this data, is “opened” for reading. This bank is then “closed” by the memory when the data in the memory is “refreshed” or when data is read from a different row of the same bank. An overhead in terms of power consumption and time is incurred whenever a bank has to be opened or closed in the memory. The existing systems do not utilize the bank structure of memory devices to speed up bus master accesses to the memory device.
In light of the preceding discussion, there exists a need for an efficient and cost effective memory bus bandwidth optimization system for bus master accesses. There is a requirement for a system and method that can intelligently fetch data that is likely to be used by the system in the future from the memory device. There is also a need for a system that has lower power consumption. Furthermore, there is a need for a system and method that utilizes the memory bus bandwidth in an intelligent and calculated fashion.